Single-switch flyback converter topologies are popular in many applications. In this category, quasi-resonant flyback can reduce switching loss by means of resonant operation. However, the transformer leakage energy is not recovered and clamps are needed to protect primary and secondary switches. In addition, QR flyback typically operates below 150 kHz to minimize switching losses and EMI.
FIG. 1 is a schematic illustration of a traditional active clamp flyback (ACF) converter with a secondary diode-rectifier. Lm represents the transformer magnetizing inductance, and Lr can be the leakage inductance of the transformer or the leakage inductance of the transformer in series with a discrete inductor. Capacitor Cr is the clamping capacitor and S2 is the clamping switch. S1 is same switch as traditional single-switch flyback has. D1 is the rectifier diode that conducts current to the load. Co is used to filter the switching ripple of the output voltage and has big capacitance.
The switches of the converter of FIG. 1, as well as the other converters discussed herein are driven with a controller (not shown) programmed to cause the converter to generate a voltage across the output capacitor Co using energy from an input at the node shared by capacitor Cr and inductor Lr.
Active clamp flyback (ACF) is a two-switch topology that achieves soft switching and recovers leakage inductance energy. Continuous conduction mode (CCM) active clamp flyback, such as that shown in FIG. 1, has positive magnetizing current, and therefore has lower RMS current. However, this circuit requires an external inductor to achieve full ZVS. In addition, the secondary rectifier turn-off is hard switched.
FIG. 2 is a schematic illustration of a traditional discontinuous conduction mode (DCM) active clamp flyback (ACF) converter. In contrast to the converter of FIG. 1, the magnetizing current of discontinuous conduction mode ACF or critical conduction mode ACF of the converter illustrated in FIG. 2 swings to a negative level. This may achieve ZVS turn-on for the low-side switch and may make zero-current-switching (ZCS) turn-off of the rectifier device possible.
In order to reduce the conduction loss of the rectifier diode especially in applications with high output current, synchronous rectifier (SR) topology is often used, as illustrated in FIG. 2. The SR scheme may include, for example, turning on the SR switch S3 in response to a sensed current through or a sensed voltage across the SR switch S3 indicating that the body diode of SR switch S3 is conducting. The SR switch S3 can be a Si MOSFET or GaN HEMT and operates in the third-quadrant to bring down the voltage drop.
The SR switch is generally controlled to conduct when the body diode starts carrying current and to block when the body diode current drops to zero. Due to such factors as circuitry delay and parasitic effects, the SR switch S3 has a delayed turn-on and an early turn-off, depending on the SR controller performance and circuit parasitics. When the SR switch is turned off, its body diode starts diverting the remaining current. If the body diode still carries high current when the SR switch S3 is turned off, a reverse recovery process happens. As a result, the circuit experiences high loss, voltage ringing, and EMI noise. Therefore, the current is reduced as much as possible before the SR switch S3 is turned off. If the diode current is zero and consequently off, it is under zero-current-switching (ZCS) turn-off condition. Such operation generally has the benefits of low loss, low voltage ringing, and low EMI noise.
In order to analyze the ACF operation, the ACF topology with the switch output capacitance is redrawn in FIG. 3. The operating waveforms of a traditional ACF converter, such as that illustrated in FIG. 3, is shown in FIG. 4. The output capacitor Co is large in capacitance, as indicated by its symbol, and therefore can be treated as a constant voltage source when analyzing the circuit.
During the interval when switch S1 is in the on state, the magnetizing inductance is charged and its current (ILm=ILr) increases linearly. In addition, secondary current (Is3) is zero during the interval with switch S1 in the on state.
At the end of the interval with switch S1 in the on state, switch S1 is turned off and switch S2 is turned on. Due to the current dividing effect between the two primary capacitors Coss and the secondary capacitor Cj, the inductor current Lr quickly drops to a value (Idip) that is lower than the peak of the magnetizing current (ILm). Then, during the interval with switch S2 on (or S1 OFF interval), Lr resonates with clamping capacitor Cr and the difference between inductor Lr current (iLr) and magnetizing current iLm is delivered to the load (Is3). The inductor current can be solved as
                                          i            Lr                    ⁡                      (            t            )                          =                                            I              dip                        ⁢                          cos              ⁡                              (                                  ω                  ⁢                                                                          ⁢                  t                                )                                              +                                                                      n                  ⁢                                                                          ⁢                                      V                    o                                                  -                                                      V                    Cr                                    ⁡                                      (                    0                    )                                                              Z                        ·                          sin              ⁡                              (                                  ω                  ⁢                                                                          ⁢                  t                                )                                                                        (        1        )                                          ω          =                      1                                                            C                  r                                ·                                  L                  r                                                                    ,                  Z          =                                                    L                r                                            C                r                                                                        (        2        )            
where Idip is the initial current of iLr before the resonant process; Vo is the output capacitor Co voltage and approximately equals to the output voltage of the transformer due to low voltage drop of SR switch S3; Vcr(0) is the initial voltage of the resonant capacitor Cr, which can be solved as (3) according to charge balance of resonant capacitor Cr.
                                                        V              r                        ⁡                          (              0              )                                =                                    nV              o                        -                                                            I                  dip                                ·                                                                            L                      r                                                              C                      r                                                                                                  tan                ⁡                                  (                  θ                  )                                                                    ,                  θ          =                      π            -                                                            (                                      1                    -                    D                                    )                                ·                                  T                  s                                                            2                ⁢                                                                            L                      r                                        ⁢                                          C                      r                                                                                                                              (        3        )            
where D is the duty cycle of S1 and Ts is the switching period.
Because clamping capacitor Cr only has current during the switch S1 OFF interval, combining equations (1) and (2), and implementing the law of charge balance, shows that at the end of the switch S1 OFF interval, iLr is −Idip. If at the end of the switch S1 OFF interval iLr is more negative than the iLm minimum, then switch S3 current (ISR) is positive, as shown in FIG. 4(a). When switch S2 is turned off, switch S3 will be forced off at high current and its body diode will go through reverse recovery and cause various problems including voltage ringing, power loss, and EMI emission noise.
Reducing the clamping capacitor Cr capacitance shortens the resonant period, which makes iLr actually merge with iLm shortly, interrupting the resonance of Lr and Cr. By the end of the switch S1 OFF interval, it is possible that iLr equals or substantially equals iLm, achieving ZCS for the secondary switch S3, as shown in FIG. 4(b).
However, as indicated in FIG. 4(b), the current of synchronous rectification switch S3 (iS3) is cut off temporarily during the switch S1 OFF interval. Accordingly, the SR controller needs to turn on and off the SR switch twice during this interval. Such operation increases driving loss and causes instability of the circuit operation.
A minimum conduction time of SR switch S3 can be programmed through the SR controller to avoid the multiple turn-on issue. However, the fixed minimum on-time causes operation anomaly at light load and impacts efficiency. In addition, the amplitude of the resonant current iLr is greater in FIG. 4(b) than that in FIG. 4(a). Such operation leads to greater RMS value and increases the conduction loss of switch S2 and the transformer winding.
In summary, to achieve ZCS of the secondary SR switch, existing ACF topology with primary resonant has the drawbacks of SR multiple turn-on and high RMS value of the primary current, which leads to poor SR control performance, high driving loss, high conduction loss, and low efficiency.